What is SVP?

SVP is a research development platform being developed collaboratively by researchers in the Computer Systems Architecture Group at the University of Amsterdam in the Netherlands and partners. It is intended as a vehicle for exploring ideas about the implementation of compiler and run-time systems for programming languages for future multi- and many-core chips.

We anticipate the main challenges for language implementors will be fine-grained control over the hardware and machine models suitable for fine-grain resource management, especially to deal with on-chip latency tolerance, and heterogeneity in processors and systems. We have proposed a radically different way of exposing the machine interface to address these challenges.

Our implementations demonstrate our proposal, for “proof of concept”, and for giving us a concrete foundation with which to extend our research in this area.

What is the Microgrid?

The Microgrid is an architecture model which demonstrates a possible many-core chip embedding the SVP interfaces in hardware. We use it as one of the foundations for our experimentation work on SVP, and for teaching activities.

What is the "SVP model"?

The SVP model is the machine model assumed by programs that use the SVP interfaces. This exposes hardare as virtual clusters of cores which accept “active messages” for bulk thread creation, remote synchronization, and low-latency point-to-point communication between threads.

Who participates in this project?

SVP has been under development since 2004 mostly by researchers from the University of Amsterdam and partners. See also our list of contributors and Community.

What are your plans for the future?

We would like SVP to have substantive impact on the design of future many-core chip architectures and their operating systems.We plan to invest the manpower required to target our platform to a wider range of hardware, while establishing partnerships with modern parallel language and operating system implementors. We will also continue with interesting research and publishing at the major systems and architecture conferences.