Academic publications

  • Jian Fu, Qiang Yang, Raphael Poss, Chris Jesshope, and Chunyuan Zhang. On-demand thread-level fault detection in a concurrent programming environment. In Proc. Intl. Conf. on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS). IEEE, Samos, Greece, July 2013.
  • Raphael Poss, Mike Lankamp, Qiang Yang, Jian Fu, Irfan Uddin, and Chris Jesshope. MGSim—a simulation environment for multi-core research and education. In Proc. Intl. Conf. on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS). IEEE, Samos, Greece, July 2013.
  • Raphael Poss, Mike Lankamp, Qiang Yang, Jian Fu, Michiel W. van Tol, Irfan Uddin, and Chris Jesshope. Apple-CORE: harnessing general-purpose many-cores with hardware concurrency management. Microprocessors and Microsystems, June 2013. ISSN 0141-9331.
  • Raphael Poss, Mike Lankamp, Qiang Yang, Jian Fu, Michiel W. van Tol, and Chris Jesshope. Apple-CORE: Microgrids of SVP cores (invited paper). In Proc. 15th Euromicro Conference on Digital System Design. IEEE Computer Society, September 2012. ISBN 978-0-7695-4798-5.
  • M. Irfan Uddin, C. Jesshope, M. W. van Tol, and R. Poss. Collecting signatures to model latency tolerance in high-level simulations of microthreaded core. In Proc. 4th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO’12). ACM, January 2012.
  • R. Poss, C. Grelck, S. Herhut, and S.-B. Scholz. Lazy reference counting for the Microgrid. In Proc. 16th Workshop on on Interaction between Compilers and Computer Architectures (INTERACT’16). IEEE, 2012.
  • R. Poss, M. Lankamp, M. Irfan Uddin, J. Sykora, and L. Kafka. Heterogeneous integration to simplify many-core architecture simulations. In Proc. 4th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO’12). ACM, January 2012.
  • Michiel W. van Tol and Chris R. Jesshope. An operating system strategy for general-purpose parallel computing on many-core architectures. Advances in Parallel Computing, High Performance Computing: From Grids and Clouds to Exascale(20):157–181, 2011. ISBN 978-1-60750-802-1. ISSN 0927-5452.
  • M. I. Uddin, M. W. van Tol, and C. R. Jesshope. High level simulation of SVP many-core systems. Parallel Processing Letters, 21(4), December 2011. ISSN 0129-6264.
  • Qiang Yang, C.R. Jesshope, and Jian Fu. A micro threading based concurrency model for parallel computing. In Proc 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW), pages 1668–1674, May 2011. ISSN 1530-2075.
  • S. Herhut, C. Joslin, S.B. Scholz, R. Poss, and C. Grelck. Concurrent non-deferred reference counting on the Microgrid: First experiences. In J. Haage and M. Morazan, editors, 22nd International Symposium on Implementation and Application of Functional Languages (IFL’10), Alphen a/d Rijn, Netherlands, Revised Selected Papers, volume 6647 of Lecture Notes in Computer Science. Springer-Verlag, Berlin, Heidelberg, New York, 2011.
  • Chris Jesshope, Michael Hicks, Mike Lankamp, Raphael Poss, and Li Zhang. Making multi-cores mainstream – from security to scalability. In Advances in Parallel Computing, volume 18. IOS Press, 2010.
  • M. Danek, L. Kafka, L. Kohout, and J. Sykora. Instruction set extensions for multi-threading in LEON3. In Z. Kotasek et al., editor, Proc. 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS’2010), pages 237–242. IEEE, 2010. ISBN 978-1-4244-6610-8.
  • Thomas Bernard, Clemens Grelck, Michael Hicks, Chris Jesshope, and Raphael Poss. Resource-agnostic programming for many-core microgrids. In Proc. 4th Workshop on Highly Parallel Pro- cessing on a Chip (HPPC 2010). Ischia - Naples, Italy, September 2010.
  • Michael A. Hicks, Michiel W. van Tol, and Chris R. Jesshope. Towards Scalable I/O on a Many- core Architecture. In International Conference on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS), pages 341–348. IEEE, July 2010. ISBN 978-1-4244-7937-5.
  • Raphael Poss and Chris Jesshope. Towards scalable implicit communication and synchronization. In The First Workshop on Advances in Message Passing (AMP’10). Toronto, Canada, June 2010.
  • K. Bousias, L. Guang, C.R. Jesshope, and M. Lankamp. Implementation and Evaluation of a Microthread Architecture. Journal of Systems Architecture, 55(3):149–161, 2009.
  • Chris Jesshope, Mike Lankamp, and Li Zhang. Evaluating CMPs and their memory architecture. In Architecture of Computing Systems – ARCS 2009, volume 5455/2009 of Lecture Notes in Computer Science, pages 246–257. Springer Berlin / Heidelberg, 2009. ISBN 978-3-642-00453-7. ISSN 0302- 9743 (Print) 1611-3349 (Online).
  • Chris Jesshope, Mike Lankamp, and Li Zhang. The Implementation of an SVP Many-core Processor and the Evaluation of its Memory Architecture. ACM SIGARCH Computer Architecture News, 37 (2):38–45, 2009. ISSN 0163-5964.
  • M. W. van Tol, C. R. Jesshope, M. Lankamp, and S. Polstra. An implementation of the SANE Virtual Processor using POSIX threads. J. Syst. Archit., 55(3):162–169, 2009. ISSN 1383-7621.
  • C.R. Jesshope. A model for the design and programming of multi-cores. Advances in Parallel Computing, High Performance Computing and Grids in Action(16):37–55, 2008. ISBN 978-1-58603- 839-7.
  • Chris Jesshope. Operating systems in silicon and the dynamic management of resources in many-core chips. Parallel Processing Letters, 18(2):257–274, 2008.
  • Chris Jesshope, Jean-Marc Philippe, and Michiel van Tol. An architecture and protocol for the management of resources in ubiquitous and heterogeneous systems based on the SVP model of concurrency. In Embedded Computer Systems: Architectures, Modeling, and Simulation, pages 218–228, 2008. ISBN 978-3-540-70549-9.
  • T. Bernard, K. Bousias, L. Guang, C. R. Jesshope, M. Lankamp, M. W. van Tol, and L. Zhang. A general model of concurrency and its implementation as many-core dynamic RISC processors. In W. Najjar and H. Blume, editors, Proc. Intl. Conf. on Embedded Computer Systems: Architecture, Modeling and Simulation (IC-SAMOS 2008), pages 1–9. IEEE, Samos, Greece, July 2008. ISBN 978-1-4244-1985-2.
  • T. D.Vu, L. Zhang, and C. R. Jesshope. The verification of the on-chip COMA cache coherence protocol. In International Conference on Algebraic Methodology and Software Technology, pages 413–429, 2008. ISBN 978-3-540-79979-5.
  • Nabil Hasasneh, Ian Bell, and Chris Jesshope. Asynchronous arbiter for micro-threaded chip multiprocessors. Journal of Systems Architecture, 53(5-6):253–262, 2007. ISSN 1383-7621.
  • Kostas Bousias, Nabil Hasasneh, and Chris Jesshope. Instruction level parallelism through microthreading – scalable approach to chip multiprocessors. The Computer Journal, 49(2):211–233, March 2006.
  • T. Bernard, K. Bousias, B. de Geus, Lankamp M., L. Zhang, A.D. Pimentel, P.M.W. Knijnenburg, and C.R. Jesshope. A microthreaded architecture and its compiler. In M. Arenez, R. Doallo, B. B. Fraguela, and J. Tourino, editors, Proc. 12th Workshop on Compilers for Parallel Computers (CPC’06), pages 326–340. University of A Coruña, A Coruña, Spain, January 2006. ISBN 54-609-8459-1.
  • C.R. Jesshope. Microthreading, a model for distributed instruction-level concurrency. Parallel Processing Letters, 16(2):209–228, 2006.
  • Ian Bell, Nabil Hasasneh, and Chris Jesshope. Supporting microthread scheduling and synchronisation in CMPs. International Journal of Parallel Programming, 34:343–381, 2006. ISSN 0885-7458.
  • A. Bolychevsky, C.R. Jesshope, and V.B. Muchnick. Dynamic scheduling in RISC architectures. IEE Trans. E, Computers and Digital Techniques, 143:309–317, 1996.

See also the related publications on the Apple-CORE web site.

Theses, reports, etc

Funding sources

Research on SVP was funded by the following projects:

ADVANCE logo Apple-CORE logo AETHER logo NWO logo